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Antmicro provides engineering services, open source tools, platforms and strategic R&D for high-tech products.
SOFTWARE
Reproducible board support packages
We use scalable open source build systems like Yocto/OpenEmbedded and Buildroot to create complete, thoroughly-tested Linux BSPs for embedded devices. Building on our experience with driver, SDK, buildsystem, secure boot and hypervisor development, as well as resources like the meta-antmicro Yocto layer and open source tools including our deployed_code_update Protoplaster BSP testing framework or deployed_code_update Remote Device Fleet Manager, we bring the capabilities Linux offers to the devices we build for our customers.
meta-antmicro Yocto layer 
SOFTWARE
Industrial Android
We're helping customers design and implement fully customizable, modern Android BSPs for industrial and consumer devices.
We offer porting services including customized boot graphics, kiosk/sandbox mode, advanced I/O interfacing,
Using Android we can provide a familiar user experience on high-performance platforms, including Nvidia Jetson, NXP i.MX and Qualcomm Snapdragon.
9:49AM
75%
battery_horiz_075SOFTWARE
OTA fleet updates and management
We build fully-featured, tailored and transparent Over-The-Air update systems for deploying packages across fleets of devices running Linux, Android and Zephyr RTOS. Targeting heterogeneous deployments with varying scale and access to connectivity, our open source solutions provide advanced features like delta updates, rollbacks or update groups and are easily deployable in your own infrastructure and CI environments.
Updates available
Firmware 1.6
Released
2024/02/12
SOFTWARE
Remote Device Fleet Manager
Modular, adjustable open source system that enables secure update deployment across various applications and operating systems, as well as model updates for edge AI contexts.
Open API for high integrability
RDFM is easily integrable with other systems, like automatic Over-The-Air update package upload from CI (GitLab, GitHub) or integration with pre-existing fleet management solutions.
Continous Integration
You can use RDFM in tandem with Continuous Integration systems for automated updates, scalable fleet management, and enhanced operational efficiency.
Linux, Android, Zephyr and more
RDFM supports a wide range of operating systems, including Linux, Android, Zephyr, and more, making it a versatile tool for managing device fleets.
Security and configurability
The tool uses JSON Web Tokens and RSA key pairs, and the management system includes OAUth2 support for controlling read/write permissions.
SOFTWARE
Building products with Zephyr RTOS
As long‑time Zephyr Project platinum members and contributors, Antmicro works with product makers and silicon vendors to take advantage of Zephyr's structuredness and configurability when adding, testing, and maintaining support for families of silicon devices and real-life products running Zephyr as the main or auxiliary OS.
96b_aerocore2 96b_argonkey 96b_avenger96 96b_neonkey
96b_nitrogen 96b_stm32_sensor_mez 96b_wistrio acn52832
adafruit_feather_m0_basic_proto adafruit_feather_m0_lora adafruit_feather_stm32f405 adafruit_grand_central_m4_express adafruit_itsybitsy_m4_express adafruit_itsybitsy_nrf52840
adafruit_kb2040 adafruit_qt_py_rp2040 adafruit_trinket_m0 adi_sdp_k1
apollo4p_blue_kxr_evb apollo4p_evb arduino_due arduino_mkrzero arduino_nano_33_ble arduino_nano_33_iot arduino_nicla_sense_me
arduino_uno_r4_minima arduino_zero
ast1030_evb az3166_iotdevkit b_g474e_dpow1 b_l072z_lrwan1 b_l4s5i_iot01a b_u585i_iot02a bbc_microbit bbc_microbit_v2
bcm958401m2
beagleconnect_freedom bl652_dvk bl653_dvk bl654_dvk bl654_sensor_board bl654_usb black_f407ve black_f407zg_pro blackpill_f401cc blackpill_f401ce blackpill_f411ce blueclover_plt_demo_v2_nrf52832 bt510 bt610 cc1352p1_launchxl cc1352r_sensortag cc1352r1_launchxl cc26x2r1_launchxl cc3220sf_launchxl cc3235sf_launchxl circuitdojo_feather_nrf9160 circuitdojo_feather_nrf9160_ns contextualelectronics_abc
cy8cproto_062_4343w cy8cproto_063_ble
cyclonev_socdk
da14695_dk_usb da1469x_dk_pro
decawave_dwm1001_dev degu_evk disco_l475_iot1 dragino_lsn50 dragino_nbsn95 ebyte_e73_tbb_nrf52832
efm32wg_stk3800 ev11l78a
faze fk7b0m1_vbt6 frdm_k22f frdm_k64f frdm_k82f frdm_kl25z frdm_kw41z
gd32a503v_eval gd32e103v_eval gd32e507v_start gd32e507z_eval gd32f350r_eval gd32f403z_eval gd32f407v_start gd32f450i_eval gd32f450v_start gd32f450z_eval gd32f470i_eval gd32l233r_eval google_dragonclaw google_twinkie_v2 holyiot_yj16019 ip_k66f
kv260_r5 lora_e5_dev_board lora_e5_mini lpcxpresso11u68 lpcxpresso51u68 lpcxpresso55s06 lpcxpresso55s16 lpcxpresso55s28 lpcxpresso55s36 mec1501modular_assy6885 mec15xxevb_assy6853 mec172xevb_assy6906 mec172xmodular_assy6930 mercury_xu mg100 mikroe_clicker_2 mikroe_mini_m4_for_stm32 mimxrt1010_evk mimxrt1015_evk mimxrt1020_evk mimxrt1024_evk mimxrt1040_evk mimxrt1062_fmurt6 mimxrt1064_evk mm_feather mm_swiftio mps2_an385 mr_canhubk3 msp_exp432p401r_launchxl
npcx4m8f_evb npcx7m6fb_evb npcx9m6f_evb nrf21540dk_nrf52840 nrf51_ble400 nrf51_blenano nrf51_vbluno51 nrf52_adafruit_feather nrf52_blenano2 nrf52_sparkfun nrf52_vbluno52 nrf52832_mdk nrf52833dk_nrf52820 nrf52833dk_nrf52833 nrf52840_blip nrf52840_mdk nrf52840_mdk_usb_dongle nrf52840_papyr nrf52840dk_nrf52811 nrf52840dk_nrf52840 nrf52840dongle_nrf52840 nrf52dk_nrf52805 nrf52dk_nrf52810 nrf52dk_nrf52832 nrf5340_audio_dk_nrf5340_cpuapp nrf5340_audio_dk_nrf5340_cpuapp_ns nrf5340_audio_dk_nrf5340_cpunet nrf5340dk_nrf5340_cpuapp nrf5340dk_nrf5340_cpuapp_ns nrf5340dk_nrf5340_cpunet nrf9131ek_nrf9131 nrf9131ek_nrf9131_ns nrf9151dk_nrf9151 nrf9151dk_nrf9151_ns nrf9160dk_nrf52840 nrf9160dk_nrf9160 nrf9160dk_nrf9160_ns nrf9161dk_nrf9161 nrf9161dk_nrf9161_ns nucleo_c031c6 nucleo_f030r8 nucleo_f031k6 nucleo_f042k6 nucleo_f070rb nucleo_f091rc nucleo_f103rb nucleo_f207zg nucleo_f302r8 nucleo_f303k8 nucleo_f303re nucleo_f334r8 nucleo_f401re nucleo_f410rb nucleo_f411re nucleo_f412zg nucleo_f413zh nucleo_f429zi nucleo_f446re nucleo_f446ze nucleo_f722ze nucleo_f746zg nucleo_f756zg nucleo_f767zi nucleo_g031k8 nucleo_g070rb nucleo_g071rb nucleo_g0b1re nucleo_g431rb nucleo_g474re nucleo_h563zi nucleo_h723zg nucleo_h743zi nucleo_h753zi nucleo_h7a3zi_q nucleo_l011k4 nucleo_l031k6 nucleo_l053r8 nucleo_l073rz nucleo_l152re nucleo_l412rb_p nucleo_l432kc nucleo_l433rc_p nucleo_l452re nucleo_l476rg nucleo_l496zg nucleo_l4a6zg nucleo_l4r5zi nucleo_l552ze_q nucleo_u575zi_q nucleo_u5a5zj_q nucleo_wb55rg nucleo_wba52cg nucleo_wba55cg nucleo_wl55jc numaker_pfm_m467
olimex_lora_stm32wl_devkit olimex_stm32_e407 olimex_stm32_h103 olimex_stm32_h405 olimex_stm32_h407 olimex_stm32_p405 olimexino_stm32 pan1770_evb pan1780_evb pan1781_evb pan1782_evb pandora_stm32l475 particle_argon particle_boron particle_xenon pinetime_devkit0 pinnacle_100_dvk
qomu quick_feather rak4631_nrf52840 rak5010_nrf52840 raytac_mdbt50q_db_33_nrf52833 raytac_mdbt50q_db_40_nrf52840 raytac_mdbt53_db_40_nrf5340_cpuapp raytac_mdbt53_db_40_nrf5340_cpuapp_ns raytac_mdbt53_db_40_nrf5340_cpunet raytac_mdbt53v_db_40_nrf5340_cpuapp raytac_mdbt53v_db_40_nrf5340_cpuapp_ns raytac_mdbt53v_db_40_nrf5340_cpunet rddrone_fmuk66 reel_board rm1xx_dvk ronoth_lodev rpi_pico ruuvi_ruuvitag rzt2m_starter_kit sam4e_xpro sam4l_ek sam4s_xplained scobc_module1 seeeduino_xiao segger_trb_stm32f407 sensortile_box sensortile_box_pro serpente sparkfun_pro_micro_rp2040 sparkfun_thing_plus_nrf9160 sparkfun_thing_plus_nrf9160_ns steval_fcu001v1 stm3210c_eval stm32373c_eval stm32f0_disco stm32f030_demo stm32f072_eval stm32f072b_disco stm32f103_mini stm32f3_disco stm32f3_seco_d23 stm32f4_disco stm32f401_mini stm32f411e_disco stm32f412g_disco stm32f429i_disc1 stm32f469i_disco stm32f723e_disco stm32f746g_disco stm32f7508_dk stm32f769i_disco stm32g0316_disco stm32g071b_disco stm32g081b_eval stm32h573i_dk stm32h735g_disco stm32h750b_dk stm32h7b3i_dk stm32l1_disco stm32l476g_disco stm32l496g_disco stm32l4r9i_disco stm32l562e_dk stm32mp157c_dk2 stm32u5a9j_dk stm32vl_disco stm32wb5mm_dk stm32wb5mmg swan_r5 teensy40 teensy41 thingy52_nrf52832 thingy53_nrf5340_cpuapp thingy53_nrf5340_cpuapp_ns thingy53_nrf5340_cpunet twr_ke18f twr_kv58f220m ubx_bmd300eval_nrf52832 ubx_bmd330eval_nrf52810 ubx_bmd340eval_nrf52840 ubx_bmd345eval_nrf52840 ubx_bmd360eval_nrf52811 ubx_bmd380eval_nrf52840 ubx_evkannab1_nrf52832 ubx_evkninab1_nrf52832 ubx_evkninab3_nrf52840 ubx_evkninab4_nrf52833 ucans32k1sic usb_kw24d512
v2m_beetle w5500_evb_pico waveshare_open103z we_ophelia1ev_nrf52805 we_proteus2ev_nrf52832 we_proteus3ev_nrf52840 weact_stm32g431_core wio_terminal xiao_ble xmc45_relax_kit xmc47_relax_kit zybo
intel_socfpga_agilex_socdk intel_socfpga_agilex5_socdk
khadas_edgev roc_rk3568_pc rpi_4b
adp_xc7k_ae350
esp32c3_devkitm gd32vf103c_starter gd32vf103v_eval
hifive1 icev_wireless
it82xx2_evb it8xxx2_evb
litex_vexriscv longan_nano m2gl025_miv
neorv32 niosv_g niosv_m
opentitan_earlgrey
riscv32_virtual sparkfun_red_v_things_plus stamp_c3
titanium_ti60_f225
tlsr9518adk80d xiao_esp32c3
generic_leon3
acrn_ehl_crb intel_adl_crb intel_adl_rvp intel_ehl_crb intel_ish_5_4_1 intel_ish_5_6_0 intel_ish_5_8_0 intel_rpl_p_crb intel_rpl_s_crb up_squared up_squared_pro_7000
Testing Zephyr in simulation at scale
Maintaining the RISC-V ISA in Zephyr
Exploring Zephyr's full potential
Terminal
*** Booting Zephyr OS build v2.6.0-rc1 ***<inf> boot: Build time: Jun 16 2024 10:00:00<inf> zephyr_boot: Zephyr RTOS boot successful!Starting Hello World demo...<inf> hello_world_demo: Hello World!Upstreaming and maintaining SoC support for silicon vendors
SOFTWARE
Automated hardware testing
We can provide you with a methodology for transparent, CI-driven full-platform testing, both for evaluating and validating newly developed support packages for custom platforms and prototypes, as well as for adding new functionalities to existing solutions. Our universal and efficient methodology is synthesized in Protoplaster, our open source testing framework for automated testing.
Device ID #5432
Device ID #5433
Device ID #5434
Device ID #5435
SOFTWARE
Streamlining video system development
From camera drivers to codecs, including an open source toolkit for computer vision projects, we provide critical building blocks for your video-based endeavors and ways to test them on hardware and in simulation. Debug your V4L2, mediapipe and gstreamer pipelines, improve video quality, and automate testing with specialized software video solutions for 360 vision, robotics, teleoperation etc.
PYRA V4L2
V4L2 development
Automating video pipeline development
Raviewer
| Color format | RGB24 |
| Endianness | BIG ENDIAN |
| Pixel format | RGBA |
| Pixel plane | PACKED |
| Bits per component: | (8, 8, 8, 0) |
Image data analysis
SOFTWARE
Open source computer vision toolkit
Based on the needs of customer and R&D projects, we have been developing an ever-growing collection of tools and libraries for computer-vision based AI use cases. Whether it's debugging ISP pipelines or controlling camera systems with Python, we can adapt existing open source tools or build them from scratch to acclerate your workflows and address the needs of your projects.
Raviewer
Open-source utility dedicated to parsing and displaying binary data acquired straight from a camera for debugging and ISP development.
Farshow
A minimalistic library for streaming frames from remote devices over UDP and displaying them live using OpenCV and ImgUI.
grabthecam
A C++ library for controlling video4linux cameras and capturing frames. The library provides low-level access to all camera properties with the convenience of a high-level API.
pyrav4l2
pyrav4l2 is a library that lets you easily control V4L2 devices inside Python scripts. It provides a high-level API for controlling camera parameters and streaming frames.
SOFTWARE
Developing distributed systems with ROS 2
For complex, distributed systems involving numerous sensors, interconnected algorithms and sophisticated flow control, we take advantage of the modularity offered by ROS 2. With experience spanning many projects with overlapping needs, we are constantly expanding our collection of custom ROS 2 nodes and combining them with other parts of our open source toolkit to help implement real-world robotics and industrial applications using computer vision and edge AI.
SOFTWARE
Security & hardening
We provide services for security hardening, Root of Trust, secure boot, encryption and more, building transparent and tailored software solutions for hardware-assisted security. We can help you adapt secure bootloaders, hypervisors and application OSs, minimize your attack surfaces by tailoring and hardening your BSP, or deploy a trusted execution environment (e.g. OP-TEE) to prevent unauthorized access or modification of applications/data and protect systems from changing external factors, unusual conditions, misuse and user errors. We're working with security down to the silicon level, building open source Root of Trust and secure ML chips with customers like Google and Microsoft.
root@secure-system:~#
Root of Trust
Click the button to run the demo
HARDWARE
A transparent hardware development process
From edge AI processing gateways to complex, high-speed multi-PCB systems, we develop complete products in an open process that keeps you in full control: no license fees, no restrictions, no vendor lock-in.
HARDWARE
Complex, multi-layer designs with detailed insight
Sophisticated devices require a sophisticated design process which Antmicro will transparently guide you through. With our software-driven open product development flow using KiCad and Blender, capable of building complex, multi-layer PCBs, you will be able to peek into the process and see how your board is taking the desired shape and form.
HARDWARE
Miniaturization
HARDWARE
High-frequency design
Antmicro’s vast experience in designing hardware and software for high-speed interfaces includes building advanced DDR or PCIe test frameworks, high-end FPGA emulation platforms for ASIC development and high-performance datacenter compute cluster designs. To ensure automated and comprehensive testing for complex, multi-layer PCB designs, we employ our simulation-based signal integrity analysis and electromagnetic interference scanning workflows.
HARDWARE
Integrating embedded vision systems
Working with camera vendors including FRAMOS, Leopard Imaging, Allied Vision, and with an extensive track-record of building embedded vision systems, Antmicro has all the means to select and integrate the right imaging solutions for your device.
Building next-gen products with NVIDIA Jetson
Integrating high-speed camera interfaces
HARDWARE
Rapid prototyping based on open designs
We use our open hardware designs portfolio to rapidly create new vision device prototypes based on NVIDIA Jetson, Qualcomm Snapdragon, NXP i.MX series, TI OMAP and other embedded platforms. With a validated proof of concept in hand, we create customized devices based on our vast component library.
HARDWARE
Full product design
Use Antmicro's cross-discipline experience to develop your next-gen product:
Our workflow, the components and frameworks we build on top of are software-driven and open source so that you can reproduce and own the complete results of our work for you.
HARDWARE
Fully traceable system design
Our design workflow, codified into a framework called System Designer, makes it easy to manage the product lifecycle of even the most advanced devices, with multi-level exploration, interconnected assets and photorealistic renders. In fast-paced, technically advanced projects, the ability to easily navigate the hardware and software co-development process in any level of detail helps catch issues early and fosters cross-team collaboration, cutting time to market.
System Designer: X-Mine Scanner
AI
AI optimization and deployment, from edge to cloud
Antmicro provides comprehensive assistance in implementing edge AI solutions in a cloud context. We help our customers with AI model development and optimization, dataset management, software and hardware co-development and deployment.
AI model development and inference optimization
Renode
Starting emulation
12:09:39.5568 [INFO] Machine started.
12:09:40.7074 [INFO] Image prediction result: id: 178
12:09:40.7100 [INFO] Memory statistics:
12:09:40.7101 [INFO] HOST_LOCAL: 50528B allocated, 150528B freed, 760937B peak
12:09:40.7102 [INFO] DEVICE_LOCAL: 60937B allocated, 150528B peak, 70B live
12:09:40.7105 [INFO] mobilenet_v1 finished successfully
ML flow, runtime and hardware testing in simulation
Software and hardware co-development and deployment
Seamless AI deployment
AWS
Azure
Google Cloud
Edge devices
Hybrid cloud
On-premise
AI
AI-Powered Computer Vision
Complex use cases require advanced models for reliable and fast vision processing, ensuring accurate, real-time insights. We provide AI solutions for computationally demanding real-time computer vision applications, which drive the need for ever more powerful embedded hardware. Using our broad open source toolkit and our deep knowledge of the ML accelerators landscape, FPGAs and embedded GPUs, we build low-latency high resolution video processing systems including stereo / 360-deg vision with multi-camera input, detection, classification, segmentation and more.
Object detection
Objects
Click to view the bounding box and mask
AI
Complete AI solutions for diverse use cases
Our AI services involve co-developing hardware, software and tooling to get the most of edge AI devices in real-world applications. Based on open source, the ML models, runtimes and platforms developed by Antmicro offer transparency, flexibility and vertical integration capabilities necessary to build best-in-class solutions for use cases varying from object detection and classification to data-driven decision-making in complex, distributed systems.
Agriculture
In modern agriculture, AI provides real-time crop monitoring for pest detection, precision irrigation management, yield prediction, QA, autonomous drone-assisted crop spraying and more; many of those tasks require capable edge AI processing devices we can help you build.
AI
Kenning
Kenning is our open source ML framework for creating deployment flows and runtimes for Deep Neural Network applications across a broad spectrum of target hardware. Kenning provides modular, unified execution blocks for training, optimization and runtime pipelines that can be used regardless of underlying frameworks.
Modular, unified execution blocks
Kenning aims towards providing unified execution blocks for Deep Neural Network training, optimization, and runtime frameworks.
Model performance analysis
You can gain insight into model performance and quality with detailed reports and model comparison with textual descriptions as well as visualizations
Seamless integration
With Kenning, you can switch between platforms for your AI flows with just a small change in code, without the need to reimplement larger parts of a project.
Runtime pipelines
Using Kenning's modular and extensible runtime components, you can quickly assemble custom pipelines tailored to your specific use case.
AI
Portable DNN applications
With Kenning you can switch between platforms for your AI flows with just a small change in code, without the need to reimplement larger parts of a project. Kenning supports DNN application deployment on a wide variety of Linux platforms such as NVIDIA Jetson series devices, SiFive RISC-V SoCs, as well as Zephyr-enabled microcontrollers and more.
Kenning
from pathlib import Path
from kenning.datasets.pet_dataset import PetDataset
from kenning.modelwrappers.classification.tensorflow_pet_dataset import TensorFlowPetDatasetMobileNetV2
from kenning.optimizers.tflite import TFLiteCompiler
from kenning.utils.resource_manager import ResourceURI
model = TensorFlowPetDatasetMobileNetV2(
ResourceURI(
"kenning:///models/classification/tensorflow_pet_dataset_mobilenetv2.h5"
),
PetDataset(Path("./pet_dataset")),
)
tflite_compiler = TFLiteCompiler(
model.dataset,
Path("./mobilenet_i8.tflite"),
inferenceinputtype="int8",
inferenceoutputtype="int8",
model_framework="keras",
)
tflite_compiler.compile(model.model_path, model.get_io_specification())
AI
Model performance analysis
Kenning provides in-depth model quality reports and comparisons with textual descriptions as well as visualizations of inference time, CPU/GPU usage, prediction quality and much more. Such thorough evaluation of model effectiveness helps us guide our customers towards informed decisions for optimal performance and efficiency.
Kenning Bare Metal IREE Runtime Accuracy
0.9574
+4%
Mean precision
0.9571
+10%
Mean sensitivity
0.9577
+0.5%
AI
Specialized Large Language Models
We develop customized, open source based LLMs that offer the best performance and accuracy for specific embedded use cases, taking into account available compute and implemented runtimes. The models we create facilitate labor-intensive tasks in specific domains, e.g. searching through HW datasheets or analyzing sensor data.
Hello, how can I assist you today?
AI
OTA AI model deployment
Using our deployed_code_update Remote Device Fleet Manager framework, we can provide not only OTA updates for entire BSPs, but also check and update AI models deployed on target machines. RDFM verifies the necessity to update models and orchestrates updates with just a quick reload required in-app. For deployed, running models, we can obtain basic statistics from predictions and model execution from each device. We can also transfer data (anonymyzed or original) to remote storages like GCP, AWS or Azure, for further processing or debugging and training purposes.
object-detection-0.1
Release v0.2
* Added detections of objects Y
* Improved overall mAP score
Camera 1
ObjectsX = 3
ObjectsY = 0
Camera 2
ObjectsX = 2
ObjectsY = 2
Camera 3
ObjectsX = 0
ObjectsY = 2
Camera 4
ObjectsX = 3
ObjectsY = 1
Camera 5
ObjectsX = 5
ObjectsY = 1
Camera 6
ObjectsX = 0
ObjectsY = 3
ASIC & FPGA
Developing open source I/O & processing cores
We create open source, reusable ASIC and FPGA IP cores portable between platforms and processes, enabling transparency, vertical integration, and uninhibited collaboration in projects such as CHIPS Alliance's Caliptra Root of Trust. We can design I/O, processing and other IP to meet the specific requirements of our customers' use cases.
Video IP cores
PCI Express
Memory controllers
A/V codecs
DMAs
AI accelerators
I/O interfaces
2D graphics accelerators
Ethernet
ASIC & FPGA
Customizing and enhancing RISC-V cores
Based on extensive RISC-V experience, we offer customization and modification services for RISC-V cores. We assist in replacing legacy cores with RISC-V, incorporating supplementary RISC-V cores into next-gen chips, and adapting existing core implementations for specialized use cases. We also work with improving the security and verification coverage of RISC-V CPUs, implementing security mitigations, CI-based code quality checks, verification and testing pipelines.
Custom Accelerators for RISC-V
| File Name | Progress | Tests |
|---|---|---|
| dma.sv | 93.4% | 15/16 |
| mem.sv | 68.8% | 33/48 |
| pmp.sv | 82.4% | 61/74 |
Testing and verification of RISC-V Cores
Extending and adapting RISC-V Cores for specialized applications
Replacing legacy cores with RISC-V
ASIC & FPGA
ASIC & FPGA developer productivity tools
Use our engineering services and expertise in creating and adapting specialized tools to boost ASIC and FPGA development productivity. We create and enhance build systems, CI and testing frameworks, IDE plugins and more to enhance developers' efficiency and performance. We help hardware teams adopt tools like Bazel for cacheable builds, Conda for tool packaging, GitLab CI and GitHub Actions for end-to-end fully customizable testing at scale, (dev)containers for reproducible workflows, and Theia/VS code for collaborative, seamless local+remote development.
IDE
module top (
input clk_i, // clock input
input rst_ni, // active low reset
input [31:0] data_i, // data input
input valid_i, // data input is valid
output logic [ 7:0] result_o, // calculated result
output logic valid_o // result is valid
);
// Delay valid by 1 clock cycle
logic valid_q;
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_delay_valid
if (~rst_ni) begin
valid_q <= '0';
end else begin
valid_q <= valid_i;
end
end
// Assign valid_q to output
assign valid_o = valid_q;
// Calculates result in 1 clock cycle
processor xprocessor (
.data_i (data_i),
.result_o(result_o)
);
endmodule : top
ASIC & FPGA
Commercial support for Verilator
We provide engineering support in customizing and extending the most popular open source RTL simulator, Verilator. We can help you adopt and adapt Verilator for specific needs, including very large and complex designs and niche use cases. Through integrating Verilator with your existing workflows, we can help you take advantage of infinite cloud scaling that open source verification and testing allows.
Verilator performance improvements
Enabling open source UVM support
ASIC & FPGA
Unified register interface definitions
To ensure consistency and interoperability in complex digital designs, we follow a standardized approach and develop tooling for defining and managing registers across various hardware components and systems. This involves describing interfaces using approaches like SystemRDL, which is a single source of truth for describing hardware register maps, addresses and memory maps. SystemRDL can be used to generate SystemVerilog, UVM Register Models, documentation, Renode functional model register defintions, IP-XACT and more, enabling hardware and software teams to collaborate more efficiently.
I3C.RDL
regfile PIOControl {
external reg {
name = "Command issue port";
field { name = "COMMAND_QUEUE_PORT"; sw = w; hw = r; }
COMMAND_DATA [31:0];
} COMMAND_PORT @ 0x0;
external reg {
name = "Command response port";
field { name = "RESPONSE_QUEUE_PORT"; sw = r; hw = w; }
RESPONSE_DATA [31:0];
} RESPONSE_PORT @ 0x4;
external reg {
name = "Transferred data access port";
field { name = "TX_DATA"; sw = w; hw = r; }
TX_DATA [31:0];
} TX_DATA_PORT @ 0x8;
external reg {
name = "Received data access port";
field { name = "RX_DATA"; sw = r; hw = w; }
RX_DATA [31:0];
} RX_DATA_PORT @ 0x8;
external reg {
name = "IBI descriptor access port";
field { name = "IBI_DATA"; sw = r; hw = w; }
IBI_DATA;
} IBI_PORT @ 0xC;
};
addrmap I3CCSR {
PIOControl PIOControl @ 0x080;
};
Generate assets
Generate assets
Generate docs, Renode model and SystemVerilog registers from SystemRDL definition
ASIC & FPGA
Design aggregation tooling
Topwrap: SoC example
ASIC & FPGA
Coverage reporting and analysis
In order to keep track of code coverage across internal and customer RTL development projects, we developed an open source Coverview tool which can process the output from industry standard HDL simulators (including but not limited to the open source Verilator), to automatically generate easy-to-read, comprehensive coverage dashboards. Coverview lets you inspect multiple coverage types at a glance or focus on specifics, embed concrete results as well as load them in runtime, link back to specific tests, and more, as shown here on the example of the VeeR EL2 project.
ASIC & FPGA
Integrating Caliptra Root of Trust
We are actively participating in the open silicon Caliptra Root of Trust project within CHIPS Alliance alongside Google, AMD, NVIDIA and Microsoft, where we are involved in RTL development, verification, tooling and CI infrastructure as well as maintenance, especially around the RISC-V VeeR-EL2 core. As part of our broader offering of memory RISC-V CPU and memory I/O processing cores development and integration, we can help you integrate the RoT IP and firmware into custom SoCs for Identity, Measured Boot and Attestation capabilities. In such projects, Antmicro can assist you with driving architectural decisions to ensure easy integration, a thorough CI-driven verification environment and use case compatibility.
Caliptra
Initializing
ASIC & FPGA
Video processing equipment and interface IP
Employing our open source hardware, IP and tooling portfolio, we develop FPGA-based solutions for video conversion, processing and streaming, targeting a variety of high-throughput interfaces such as SDI, GMSL, HDMI, USB, PCIe and MIPI CSI-2. We can rapidly prototype a wide range of video solutions and create the drivers, ISP pipelines, codec, buffering, synchronization and format conversion cores for high-end use cases including broadcasting, aerospace, industrial vision using FPGAs or FPGA SoCs.
Lattice CrossLink-NX FPGA
RENODE
Renode
Renode is a development framework which accelerates hardware product development by letting you simulate complete, complex hardware systems - including both the CPU, peripherals, sensors, environment and wired or wireless medium between nodes.
Renode supports hundreds of embedded platforms and comes with a range of developer-oriented features such as state saving and replaying, advanced hooks and events, comprehensive tracing, multi-core debugging, etc.
RENODE
Renode use cases
From simulating complex heterogeneous SoCs as well as multi-node systems, through pre-silicon and hardware-software co-development, to interactive testing and Continuous Integration workflows - Renode supports the entire development process across various use cases.
Complex system simulation
Architectural exploration
Continuous Integration
Debugging and analysis
RENODE
Simulation of complex, multi-node systems
Complex, heterogeneous multi-node setups need rigorous testing preventing possible failures, especially expensive in safety-critical applications. Renode lets you thoroughly simulate and verify multiple nodes connected via various means, like Ethernet, Bluetooth, UART, CAN, USB etc. We help our customers in the transition towards software-based testing and streamlining the development process for complex applications, including robotics, space and automotive.
RENODE
Plug-and-play building blocks
Renode lets you assemble custom hardware setups from reusable and configurable models. Freely combine CPUs, I/O and other peripherals as well as sensors into hierarchical systems, and reuse common models between related platforms. With Renode you can easily support device families and explore architecture variations just by changing the configuration in your .repl (Renode platform) file.
STM32F412.repl
| 1 | fsmcBank1: Memory.MappedMemory @ sysbus 0x60000000 |
| 2 | size: 0x10000000 |
| 3 | |
| 4 | sram: Memory.MappedMemory @ sysbus 0x20000000 |
| 5 | size: 0x00040000 |
| 6 | |
| 7 | flash: Memory.MappedMemory @ sysbus 0x08000000 |
| 8 | size: 0x200000 |
| 9 | |
| 10 | flash_controller: MTD.STM32F4_FlashController @ { |
| 11 | sysbus 0x40023C00; |
| 12 | sysbus new Bus.BusMultiRegistration { address: 0x1FFFC000; size: 0x100; region: "optionBytes" } |
| 13 | } |
| 14 | |
| 15 | usart1: UART.STM32_UART @ sysbus <0x40011000, +0x100> |
| 16 | IRQ -> nvic@37 |
| 17 | |
| 18 | usart2: UART.STM32_UART @ sysbus <0x40004400, +0x100> |
| 19 | IRQ -> nvic@38 |
| 20 | |
| 21 | usart3: UART.STM32_UART @ sysbus <0x40004800, +0x100> |
| 22 | IRQ -> nvic@39 |
| 23 | |
| 24 | uart4: UART.STM32_UART @ sysbus <0x40004C00, +0x100> |
| 25 | IRQ -> nvic@52 |
| 26 | |
| 27 | uart5: UART.STM32_UART @ sysbus <0x40005000, +0x100> |
| 28 | IRQ -> nvic@53 |
| 29 | |
| 30 | usart6: UART.STM32_UART @ sysbus <0x40011400, +0x400> |
| 31 | IRQ -> nvic@71 |
| 32 | |
| 33 | can1: CAN.STMCAN @ sysbus <0x40006400, +0x400> |
| 34 | [0-3] -> nvic@[19-22] |
| 35 | |
| 36 | can2: CAN.STMCAN @ sysbus <0x40006800, +0x400> |
| 37 | [0-3] -> nvic@[63-66] |
| 38 | master: can1 |
| 39 | |
| 40 | nvic: IRQControllers.NVIC @ sysbus 0xE000E000 |
| 41 | priorityMask: 0xF0 |
| 42 | systickFrequency: 72000000 |
| 43 | IRQ -> cpu@0 |
| 44 | |
| 45 | cpu: CPU.CortexM @ sysbus |
| 46 | cpuType: "cortex-m4f" |
| 47 | nvic: nvic |
| 48 | |
| 49 | pwr: Miscellaneous.STM32_PWR @ sysbus 0x40007000 |
| 50 | |
| 51 | crc: CRC.STM32_CRC @ sysbus 0x40023000 |
| 52 | series: STM32Series.F4 |
| 53 | |
| 54 | exti: IRQControllers.STM32F4_EXTI @ sysbus 0x40013C00 |
| 55 | numberOfOutputLines: 24 |
| 56 | [0-4] -> nvic@[6-10] |
| 57 | [5-9] -> nvicInput23@[0-4] |
| 58 | [10-15] -> nvicInput40@[0-5] |
| 59 | [16, 17, 18, 22] -> nvic@[1, 41, 42, 3] |
| 60 | |
| 61 | nvicInput23: Miscellaneous.CombinedInput @ none |
| 62 | numberOfInputs: 5 |
| 63 | -> nvic@23 |
| 64 | |
| 65 | nvicInput40: Miscellaneous.CombinedInput @ none |
| 66 | numberOfInputs: 6 |
| 67 | -> nvic@40 |
| 68 | |
| 69 | gpioPortA: GPIOPort.STM32_GPIOPort @ sysbus <0x40020000, +0x400> |
| 70 | modeResetValue: 0xA8000000 |
| 71 | pullUpPullDownResetValue: 0x64000000 |
| 72 | numberOfAFs: 16 |
| 73 | [0-15] -> exti@[0-15] |
| 74 | |
| 75 | gpioPortB: GPIOPort.STM32_GPIOPort @ sysbus <0x40020400, +0x400> |
| 76 | modeResetValue: 0x00000280 |
| 77 | outputSpeedResetValue: 0x000000C0 |
| 78 | pullUpPullDownResetValue: 0x00000100 |
| 79 | numberOfAFs: 16 |
| 80 | [0-15] -> exti@[0-15] |
| 81 | |
| 82 | gpioPortC: GPIOPort.STM32_GPIOPort @ sysbus <0x40020800, +0x400> |
| 83 | numberOfAFs: 16 |
| 84 | [0-15] -> exti@[0-15] |
| 85 | |
| 86 | gpioPortD: GPIOPort.STM32_GPIOPort @ sysbus <0x40020C00, +0x400> |
| 87 | numberOfAFs: 16 |
| 88 | [0-15] -> exti@[0-15] |
| 89 | |
| 90 | gpioPortE: GPIOPort.STM32_GPIOPort @ sysbus <0x40021000, +0x400> |
| 91 | numberOfAFs: 16 |
| 92 | [0-15] -> exti@[0-15] |
| 93 | |
| 94 | gpioPortF: GPIOPort.STM32_GPIOPort @ sysbus <0x40021400, +0x400> |
| 95 | numberOfAFs: 16 |
| 96 | [0-15] -> exti@[0-15] |
| 97 | |
| 98 | ethernet: Network.SynopsysEthernetMAC @ sysbus 0x40028000 |
| 99 | -> nvic@61 |
| 100 | |
| 101 | rom1: Memory.MappedMemory @ sysbus 0x1FFF0000 |
| 102 | size: 0xC000 |
| 103 | |
| 104 | rom2: Memory.MappedMemory @ sysbus 0x1FFFC400 |
| 105 | size: 0x3C00 |
| 106 | |
| 107 | spi1: SPI.STM32SPI @ sysbus 0x40013000 |
| 108 | |
| 109 | spi2: SPI.STM32SPI @ sysbus 0x40003800 |
| 110 | IRQ->nvic@35 |
| 111 | DMARecieve->dma1@3 |
| 112 | |
| 113 | spi3: SPI.STM32SPI @ sysbus 0x40003C00 |
| 114 | |
| 115 | spi5i2s5: SPI.STM32SPI @ sysbus 0x40015000 |
| 116 | IRQ -> nvic@85 |
| 117 | |
| 118 | i2c1: I2C.STM32F4_I2C @ sysbus 0x40005400 |
| 119 | EventInterrupt -> nvic@31 |
| 120 | ErrorInterrupt -> nvic@32 |
| 121 | |
| 122 | i2c2: I2C.STM32F4_I2C @ sysbus 0x40005800 |
| 123 | EventInterrupt -> nvic@33 |
| 124 | ErrorInterrupt -> nvic@34 |
| 125 | |
| 126 | i2c3: I2C.STM32F4_I2C @ sysbus 0x40005C00 |
| 127 | EventInterrupt -> nvic@72 |
| 128 | ErrorInterrupt -> nvic@73 |
| 129 | |
| 130 | i2cfmp1: I2C.STM32F7_I2C @ sysbus 0x40006000 |
| 131 | EventInterrupt -> nvic@95 |
| 132 | ErrorInterrupt -> nvic@96 |
| 133 | |
| 134 | dma1: DMA.STM32DMA @ sysbus 0x40026000 |
| 135 | [0-7] -> nvic@[11-17,47] |
| 136 | |
| 137 | dma2: DMA.STM32DMA @ sysbus 0x40026400 |
| 138 | [0-7] -> nvic@[56-60,68-70] |
| 139 | |
| 140 | rng: Miscellaneous.STM32F4_RNG @ sysbus 0x50060800 |
| 141 | -> nvic@80 |
| 142 | |
| 143 | iwdg: Timers.STM32_IndependentWatchdog @ sysbus 0x40003000 |
| 144 | frequency: 32000 |
| 145 | windowOption: false |
| 146 | defaultPrescaler: 0x4 |
| 147 | |
| 148 | rtc: Timers.STM32F4_RTC @ sysbus 0x40002800 |
| 149 | AlarmIRQ -> nvic@41 |
| 150 | |
| 151 | rcc: Miscellaneous.STM32F4_RCC @ sysbus 0x40023800 |
| 152 | rtcPeripheral: rtc |
| 153 | |
| 154 | timer1: Timers.STM32_Timer @ sysbus 0x40010000 |
| 155 | -> nvic@25 |
| 156 | frequency: 10000000 |
| 157 | initialLimit: 0xFFFF |
| 158 | |
| 159 | timer2: Timers.STM32_Timer @ sysbus 0x40000000 |
| 160 | -> nvic@28 |
| 161 | frequency: 50000000 |
| 162 | initialLimit: 0xFFFFFFFF |
| 163 | |
| 164 | timer3: Timers.STM32_Timer @ sysbus 0x40000400 |
| 165 | -> nvic@29 |
| 166 | frequency: 50000000 |
| 167 | initialLimit: 0xFFFF |
| 168 | |
| 169 | timer4: Timers.STM32_Timer @ sysbus 0x40000800 |
| 170 | -> nvic@30 |
| 171 | frequency: 50000000 |
| 172 | initialLimit: 0xFFFF |
| 173 | |
| 174 | timer5: Timers.STM32_Timer @ sysbus 0x40000C00 |
| 175 | -> nvic@50 |
| 176 | frequency: 50000000 |
| 177 | initialLimit: 0xFFFFFFFF |
| 178 | |
| 179 | timer6: Timers.STM32_Timer @ sysbus 0x40001000 |
| 180 | -> nvic@54 |
| 181 | frequency: 50000000 |
| 182 | initialLimit: 0xFFFF |
| 183 | |
| 184 | timer7: Timers.STM32_Timer @ sysbus 0x40001400 |
| 185 | -> nvic@55 |
| 186 | frequency: 50000000 |
| 187 | initialLimit: 0xFFFF |
| 188 | |
| 189 | timer8: Timers.STM32_Timer @ sysbus 0x40010400 |
| 190 | -> nvic@44 |
| 191 | frequency: 10000000 |
| 192 | initialLimit: 0xFFFF |
| 193 | |
| 194 | timer9: Timers.STM32_Timer @ sysbus 0x40014000 |
| 195 | -> nvic@24 |
| 196 | frequency: 10000000 |
| 197 | initialLimit: 0xFFFF |
| 198 | |
| 199 | timer10: Timers.STM32_Timer @ sysbus 0x40014400 |
| 200 | -> nvic@25 |
| 201 | frequency: 10000000 |
| 202 | initialLimit: 0xFFFF |
| 203 | |
| 204 | timer11: Timers.STM32_Timer @ sysbus 0x40014800 |
| 205 | -> nvic@26 |
| 206 | frequency: 10000000 |
| 207 | initialLimit: 0xFFFF |
| 208 | |
| 209 | timer12: Timers.STM32_Timer @ sysbus 0x40001800 |
| 210 | -> nvic@43 |
| 211 | frequency: 50000000 |
| 212 | initialLimit: 0xFFFF |
| 213 | |
| 214 | timer13: Timers.STM32_Timer @ sysbus 0x40001C00 |
| 215 | -> nvic@44 |
| 216 | frequency: 50000000 |
| 217 | initialLimit: 0xFFFF |
| 218 | |
| 219 | timer14: Timers.STM32_Timer @ sysbus 0x40002000 |
| 220 | -> nvic@45 |
| 221 | frequency: 50000000 |
| 222 | initialLimit: 0xFFFF |
| 223 | |
| 224 | bitbandPeripherals: Miscellaneous.BitBanding @ sysbus <0x42000000, +0x2000000> |
| 225 | peripheralBase: 0x40000000 |
| 226 | |
| 227 | bitbandSram: Miscellaneous.BitBanding @ sysbus <0x22000000, +0x200000> |
| 228 | peripheralBase: 0x20000000 |
| 229 | |
| 230 | sysbus: |
| 231 | init: |
| 232 | ApplySVD @https://dl.antmicro.com/projects/renode/svd/STM32F40x.svd.gz |
| 233 | Tag <0x40021000, 0x40021003> "GPIOE_MODER" 0xFFFFFFFF |
| 234 | Tag <0x40021004, 0x40021007> "GPIOE_OTYPER" 0x00000008 |
| 235 | Tag <0x50000010, 0x5000003f> "USB:RESET" 0x80000000 |
| 236 | Tag <0xA0001000, 0xA0001FFF> "QuadSPI_control_register" |
| 237 | Tag <0xA0000000, 0xA0000FFF> "FSMC_control_register" |
| 238 | Tag <0x90000000, 0x9FFFFFFF> "QuadSPI" |
| 239 | Tag <0x50000000, 0x5003FFFF> "USB_OTG_FS" |
| 240 | Tag <0x40016000, 0x400163FF> "DFSDM1" |
| 241 | Tag <0x40012C00, 0x40012FFF> "SDIO" |
| 242 | Tag <0x40002C00, 0x40002FFF> "WWDG" |
RENODE
Simulating heterogeneous multi-core systems
RISC-V
RV32 IMAC
ARM
CORTEX-A53
ARM
CORTEX-M23
RENODE
Configurable RISC‑V support
.repl
cpu: CPU.RiscV32 @ sysbus cpuType: "rv32im"
Architecture
ISA sets
ISA extensions
RENODE
Pre-silicon development and architectural exploration
Renode's pre-silicon simulation capabilities allow users to make the right architectural decisions in the SoC development process by providing the means to quickly evaluate changes or additions to the design. Renode also enables building automated testing suites for pre-silicon validation and early firmware development. Co-simulation with both hardware emulators and RTL simulators is a core feature in this use case, and features like trace-based modelling provide additional insight on top of what traditional functional simulation would achieve. With the freedom offered by the open source licensing model of Renode, your pre-silicon platform can be potentially freely shared with your customers if you so desire.
I2C x2
UART x2
DMA x2
ARM Cortex-M33 32-bit
SPI x3
ADC x4
RENODE
Co-simulation capabilities
Renode supports HW/SW co-simulation with Verilator as well as other DPI-capable simulators. Co-simulated components can range from I/O to CPUs, with a lot of flexibility to support development early in the product life-cycle. SystemC support and physical FPGA co-simulation are also possible, to enable the ultimate mixed fidelity development environment combining the speed and power of functional simulation with the precision of cycle accurate simulation directly from RTL.
RENODE
Deterministic testing
Renode enables fully deterministic simulation and testing of complex multi-core and multi-node systems. With feratures like footprint Execution tracing and State-saving and loading, Renode provides the tools and automation capabilities for ensuring repeatable and scalable testing. This includes a configurable virtual time flow with the ability to control external simulation and modelling tools, support for Robot and other testing frameworks, as well as other methods of integration including a Python interface.
Renode
Run STM32F427 Robot test
Run robot tests for STM32F427 Timer and I2C
RENODE
Reactive scripting with Python hooks
Renode offers various event sources for creating hooks with Python scripts, without modifying your sources. Hooks can react to changing simulation states or affect the Renode simulation itself for the purpose of debugging, error injection, etc. They enable attaching complex additional logic to selected events to support individual use cases.
code
1 #define SHUTDOWN_THRESHOLD 140
2 #define FAN_THRESHOLD 40
3 while (1) {
4 uint32_t temp = bmp180_read_temp();
5 if( temp >= SHUTDOWN_THRESHOLD ) {
6 trigger_system_action(SHUTDOWN);
7 abort();
8 } else if( temp >= FAN_THRESHOLD ) {
9 trigger_system_action(FAN_ON);
10 } else {
11 trigger_system_action(FAN_OFF);
12 } 13 thread_yield();
14 }hook
cpu.AddHook "trigger_system_action"
action_id = cpu.GetRegister(1).RawValue
temperature = machine['i2c1.bmp180'].Temperature
actions = {0: "FAN_OFF", 2: "FAN_ON", 3: "SHUTDOWN"}
if action_id == 3: # SHUTDOWN
timestamp = emulation.ElapsedVirtualTime.TotalSeconds
machine["flash"].StoreDoubleWord(0x1000, timestamp)
cpu.InfoLog("Triggered action %s, current temperature %d C" % (actions(action_id), temperature))
log
RENODE
Processing multiple streams of sensor data
Renode helps developers model sensors and test various data channels precisely in real-time using Renode Sensor Data Format. RESD enables input from multiple sensors (thermometers, humidity sensors, accelerometers, microphones, cameras etc.) to be fed into the simulated system in a coordinated way and a strictly time-controlled fashion.
Sensor data
Renode
| Time | Temperature | Humidity | Pressure |
|---|
RENODE
Tracing
Renode provides detailed insight into what exactly is happening on the simulated hardware, allowing for full inspection of the behavior of your system. You can see what the CPU does at any given time without instrumenting your application or using specialized hardware and being limited by buffer capacity. Renode also lets you display a trace of the guest application's execution in the form of an interactive flamegraph, making it easy inspect the relation between function calls and execution time and optimize your code accordingly.
RENODE
Cache usage analysis
Renode
CPU
d-cache
i-cache
Memory
| Type | Hits | Misses | Hit Rate (%) |
|---|---|---|---|
| Data Cache | 0 | 0 | 0.00 |
| Instruction Cache | 0 | 0 | 0.00 |
RENODE
Inspecting network traffic
Renode can simulate multi-device networks, and its integration with Wireshark provides visibility into the virtual network traffic by capturing and displaying packet data including content, timing and protocol details from both wired and wireless network interfaces.
This helps in assessing network utilization, protocol implementation testing and debugging as well as traffic auditing for security analysis.
Renode
Renode
Wireshark
| No | Source | Destination | Protocol | Length |
|---|
CLOUD
Datacenter Hardware
We provide complex hardware solutions for datacenters, including hybrid compute cloud infrastructure, server nodes and baseboards, hardware-in-the-loop testing rigs, BMCs and more. Building on top of our open source reference designs including GPU clusters, ARM, RISC-V and x86-based compute nodes, we help our customer architect and deploy scalable and secure compute for the most demanding workloads like AI, 3D rendering and more.
CLOUD
Infrastructure as Code
We help customers harness the Infrastructure as Code (IaC) paradigm to build reproducible, scalable and efficient cloud setups using tools including Ansible, Terraform/OpenTofu and Docker. We support the full lifecycle of IaC deployment, from requirements gathering and customizing setups/tools, through abstracting elements, modularizing infrastructure configurations, creating definition files and provisioning applications, integrating with testing in CI/CD pipelines to managing versioning and documentation and mitigating configuration drift.
Infrastructure
CLOUD
Remote hardware-in-the-loop testing
We build highly automated CI setups with hardware in the loop using tools like Protoplaster, to complement simulation-based testing with our deployed_code_update Renode framework. Hardware-in-the-loop testing is especially useful for complex FPGA, ASIC, robotics and space systems that we often work with.
CI/CD Hardware
| Status | Pipeline | Commit | Stages | Time | |
|---|---|---|---|---|---|
| check_circle | #1237 | Improve Ethernet MAC address handling | buildtestdeploy | 2024-03-15 13:45 5m 23s | |
| error | #1236 | Introduce Ethernet loopback tests | buildtest | 2024-03-15 13:30 3m 12s | |
| check_circle | #1235 | Optimize OpenFPGALoader flash speed | buildtestdeploy | 2024-03-15 13:15 5m 45s | |
| check_circle | #1234 | Allow for JTAG frequency configuration | buildtestdeploy | 2024-03-15 13:00 6m 10s |
Data Center RDIMM DDR5 Tester
Test log
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Detected RDIMM. Initializing RCD and running Host->RCD training
RCD manufacturer: b380
RCD type: 80
RCD rev: 33
Switching DFI to 1N mode
Subchannel:A CS training
Rank: 0 |
Initial scan|11111111111111111111111111111110
shift 0101|00000000000000000000000000000000|11111111111111111111111111111110|
Rank delays: 0:31
Coarse adjustment:15
CA line: 0 |00000000000000000000000000000000|00000000000000000011111111111110|
Rank delays: 0:31
Coarse adjustment:15
CA line: 0 |00000000000000000000000000000000|00000000000000000000000000000000|
CA training
DDR5 module has 7 address lines
Rank: 0
CA line: 0 |00000000000000000000000000000000|00000000000000000011111111111110|
CA[0] 18:31
CA line: 1 |00000000000000000000000000000000|00000000000000000011111111111111|
CA[1] 18:32
CA line: 2 |00000000000000000000000000000000|00000000000000000011111111111110|
CA[2] 18:31
CA line: 3 |00000000000000000000000000000000|00000000000000000011111111111111|
CA[3] 18:32
CA line: 4 |00000000000000000000000000000000|00000000000000000011111111111111|
CA[4] 18:32
CA line: 5 |00000000000000000000000000000000|00000000000000000001111111111111|
CA[5] 19:32
CA line: 6 |00000000000000000000000000000000|00000000000000000011111111111111|
CA[6] 18:32
Subchannel:B CS training
Rank: 0 |
Initial scan|10000000000000000000000000000000
Changing polarization |00111111111111111111111111111111|00000000000000000000000000000000|
Rank delays: 2:32
Coarse adjustment:17
CA line: 0 |00000000000000000000000000000000|00000000000000000111111111111110|
Rank delays: 2:32
Coarse adjustment:17
CA line: 0 |00000000000000000000000000000000|00000000000000000000000000000000|
CA training
DDR5 module has 7 address lines
Rank: 0
CA line: 0 |00000000000000000000000000000000|00000000000000000111111111111110|
CA[0] 17:31
CA line: 1 |00000000000000000000000000000000|00000000000000000011111111111111|
CA[1] 18:32
CA line: 2 |00000000000000000000000000000000|00000000000000000011111111111110|
CA[2] 18:31
CA line: 3 |00000000000000000000000000000000|00000000000000000011111111111111|
CA[3] 18:32
CA line: 4 |00000000000000000000000000000000|00000000000000000001111111111111|
CA[4] 19:32
CA line: 5 |00000000000000000000000000000000|00000000000000000011111111111111|
CA[5] 18:32
CA line: 6 |00000000000000000000000000000000|00000000000000000111111111111100|
CA[6] 17:30
Subchannel:A Timings
Rank: 0: min delay 0, max delay 31, center 15
Rank: 1: min delay 0, max delay 31, center 15
CA line: 0: min delay 18, max delay 31, center 24
CA line: 1: min delay 18, max delay 32, center 25
CA line: 2: min delay 18, max delay 31, center 24
CA line: 3: min delay 18, max delay 32, center 25
CA line: 4: min delay 18, max delay 32, center 25
CA line: 5: min delay 19, max delay 32, center 25
CA line: 6: min delay 18, max delay 32, center 25
Subchannel:B Timings
Rank: 0: min delay 2, max delay 32, center 17
Rank: 1: min delay 2, max delay 32, center 17
CA line: 0: min delay 17, max delay 31, center 24
CA line: 1: min delay 18, max delay 32, center 25
CA line: 2: min delay 18, max delay 31, center 24
CA line: 3: min delay 18, max delay 32, center 25
CA line: 4: min delay 19, max delay 32, center 25
CA line: 5: min delay 18, max delay 32, center 25
CA line: 6: min delay 17, max delay 30, center 23
Max center point delay:25, min center point delay:15, spread:10
Adjusting clock delay, so min center point is at delay 0
New clock delay:17
Subchannel:A Adjusted Tick_offsetgs
Rank: 0 center point delay: 0
Rank: 1 center point delay: 0
CA: 0 center point delay: 9
CA: 1 center point delay:10
CA: 2 center point delay: 9
CA: 3 center point delay:10
CA: 4 center point delay:10
CA: 5 center point delay:10
CA: 6 center point delay:10
Subchannel:B Adjusted Tick_offsetgs
Rank: 0 center point delay: 2
Rank: 1 center point delay: 2
CA: 0 center point delay: 9
CA: 1 center point delay:10
CA: 2 center point delay: 9
CA: 3 center point delay:10
CA: 4 center point delay:10
CA: 5 center point delay:10
CA: 6 center point delay: 8
Re-scan CS/CA
Subchannel:A
Rank: 0 |
Initial scan|11111111111111100000000000000000
shift 0101|00000000000000000111111111111111|11111111111111100000000000000000|
Rank: 1 |
Initial scan|00000000000000000000000000000000
Change polarization |00000000000000000000000000000000|00000000000000000000000000000000|
CA line: 0 |00000000000000000000000000000000|00011111111111111000000000000000|
CA line: 1 |00000000000000000000000000000000|00011111111111111000000000000000|
CA line: 2 |00000000000000000000000000000000|00011111111111110000000000000000|
CA line: 3 |00000000000000000000000000000000|00001111111111111000000000000000|
CA line: 4 |00000000000000000000000000000000|00001111111111111000000000000000|
CA line: 5 |00000000000000000000000000000000|00001111111111111000000000000000|
CA line: 6 |00000000000000000000000000000000|00011111111111111000000000000000|
Subchannel:B
Rank: 0 |
Initial scan|00000000000000000000111111111111|11111111111111111100000000000000|
Rank: 1 |
Initial scan|00000000000000000000000000000000
Change polarization |00000000000000000000000000000000|00000000000000000000000000000000|
CA line: 0 |00000000000000000000000000000000|00011111111111110000000000000000|
CA line: 1 |00000000000000000000000000000000|00011111111111111000000000000000|
CA line: 2 |00000000000000000000000000000000|00011111111111111000000000000000|
CA line: 3 |00000000000000000000000000000000|00011111111111111000000000000000|
CA line: 4 |00000000000000000000000000000000|00011111111111111000000000000000|
CA line: 5 |00000000000000000000000000000000|00011111111111111000000000000000|
CA line: 6 |00000000000000000000000000000000|00111111111111100000000000000000|
Subchannel:A CS training
Rank: 0 |
Initial scan|1111111111111111111111111111110000000000000000000000000000000000
shift 0101|0000000000000000000000000000000000001111111111111111111111111111|1111111111111111111111111111110000000000000000000000000000000000|
Rank delays: -28:30
Coarse adjustment:1
CA line: 0 |0000000000000000000000000000000000000011111111111111111111111111|1111111111111111111111111111100000000000000000000000000000000000|
CA training
DDR5 module has 1 address lines
Rank: 0
CA line: 0 |0000000000000000000000000000000000000011111111111111111111111111|1111111111111111111111111111100000000000000000000000000000000000|
CA[0] -26:29
Subchannel:A Timings
Rank: 0: min delay -28, max delay 30, center 1
CA line: 0: min delay -26, max delay 29, center 1
Max center point delay: 1, min center point delay: 1, spread: 0
Adjusting clock delay, so min center point is at delay 0
New clock delay:63
Subchannel:A Adjusted Tick_offsetgs
Rank: 0 center point delay: 0
CA: 0 center point delay: 0
Re-scan CS/CA
Subchannel:A
Rank: 0 |
Initial scan|1111111111111111111111111111100000000000000000000000000000000000
shift 0101|0000000000000000000000000000000000011111111111111111111111111111|1111111111111111111111111111100000000000000000000000000000000000|
CA line: 0 |0000000000000000000000000000000000000111111111111111111111111111|1111111111111111111111111111000000000000000000000000000000000000|
Subchannel:B CS training
Rank: 0 |
Initial scan|1111111111111111111111111111110000000000000000000000000000000000
shift 0101|0000000000000000000000000000000000001111111111111111111111111111|1111111111111111111111111111110000000000000000000000000000000000|
Rank delays: -28:30
Coarse adjustment:1
CA line: 0 |0000000000000000000000000000000000000011111111111111111111111111|1111111111111111111111111100000000000000000000000000000000000000|
CA training
DDR5 module has 1 address lines
Rank: 0
CA line: 0 |0000000000000000000000000000000000000011111111111111111111111111|1111111111111111111111111100000000000000000000000000000000000000|
CA[0] -26:26
Subchannel:B Timings
Rank: 0: min delay -28, max delay 30, center 1
CA line: 0: min delay -26, max delay 26, center 0
Max center point delay: 1, min center point delay: 0, spread: 1
Adjusting clock delay, so min center point is at delay 0
New clock delay: 0
Subchannel:B Adjusted Tick_offsetgs
Rank: 0 center point delay: 1
CA: 0 center point delay: 0
Re-scan CS/CA
Subchannel:B
Rank: 0 |
Initial scan|1111111111111111111111111111110000000000000000000000000000000000
shift 0101|0000000000000000000000000000000000001111111111111111111111111111|1111111111111111111111111111110000000000000000000000000000000000|
CA line: 0 |0000000000000000000000000000000000000011111111111111111111111111|1111111111111111111111111100000000000000000000000000000000000000|
Switching DRAM on channel:A rank:0 to 1N mode
Switching DRAM on channel:B rank:0 to 1N mode
1N mode setup
Enumerating rank: 0
Enumerating subchannel:A
module: 0
module: 1
module: 2
module: 3
Enumerating subchannel:B
module: 0
module: 1
module: 2
module: 3
Checking rank: 0
Checking subchannel:A
Base line: pass
module: 0 pass
module: 1 pass
module: 2 pass
module: 3 pass
Checking subchannel:B
Base line: pass
module: 0 pass
module: 1 pass
module: 2 pass
module: 3 pass
Subchannel:A Read training
Training rank 0
Training module 0
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000000000000000033|
25|33333300000000000000000000000000|
eye_width: 8; eye center: cycle:25,delay: 2
Training module 1
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000000000000113333|
25|33310000000000000000000000000000|
eye_width: 7; eye center: cycle:24,delay:31
Training module 2
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000000001133333333|
25|00000000000000000000000000000000|
eye_width: 8; eye center: cycle:24,delay:28
Training module 3
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000033333330000000|
eye_width: 7; eye center: cycle:24,delay:21
Channel:A rank: 0 module: 0 serial number: 0x0000000000
Channel:A rank: 0 module: 1 serial number: 0x0000000000
Channel:A rank: 0 module: 2 serial number: 0x0000000000
Channel:A rank: 0 module: 3 serial number: 0x0000000000
Subchannel:B Read training
Training rank 0
Training module 0
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000003333333000000|
eye_width: 7; eye center: cycle:24,delay:22
Training module 1
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000000000113333330|
eye_width: 6; eye center: cycle:24,delay:28
Training module 2
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000000000000000003|
25|33333300000000000000000000000000|
eye_width: 7; eye center: cycle:25,delay: 2
Training module 3
Read preamble starts in cycle:24
Data scan:
23|00000000000000000000000000000000|
24|00000000000000000000000000000000|
25|00333330000000000000000000000000|
eye_width: 5; eye center: cycle:25,delay: 4
Channel:B rank: 0 module: 0 serial number: 0x0000000000
Channel:B rank: 0 module: 1 serial number: 0x0000000000
Channel:B rank: 0 module: 2 serial number: 0x0000000000
Channel:B rank: 0 module: 3 serial number: 0x0000000000
Subchannel:A Write leveling
WL m: 0
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00000000011111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000000000011111111|
Final timing values: cycles:21(adjusted 21) delay: 0
WL m: 1
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00000001111111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000000001111111111|
Final timing values: cycles:20(adjusted 20) delay:30
WL m: 2
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00000011111111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000000011111111111|
Final timing values: cycles:20(adjusted 20) delay:29
WL m: 3
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00011111111111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000011111111111111|
Final timing values: cycles:20(adjusted 20) delay:26
DQ write training
m 0|Best Vref:34
Data scan:
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000000000013333333|
23|33330000000000000000000000000000|
m 0|start cycle:22, delay:25; end cycle:23, delay: 4|eye_width:11; eye center: cycle:22,delay:30
m 1|Best Vref:3a
Data scan:
17|00000000000000000000000000000000|
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000000001133333333|
23|30000000000000000000000000000000|
m 1|start cycle:22, delay:24; end cycle:23, delay: 1|eye_width: 9; eye center: cycle:22,delay:28
m 2|Best Vref:39
Data scan:
17|00000000000000000000000000000000|
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000000013333333333|
23|00000000000000000000000000000000|
m 2|start cycle:22, delay:22; end cycle:23, delay: 0|eye_width:10; eye center: cycle:22,delay:27
m 3|Best Vref:37
Data scan:
17|00000000000000000000000000000000|
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000013333333333300|
m 3|start cycle:22, delay:19; end cycle:22, delay:30|eye_width:11; eye center: cycle:22,delay:24
Subchannel:B Write leveling
WL m: 0
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00001111111111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000011111111111111|
Final timing values: cycles:20(adjusted 20) delay:26
WL m: 1
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00000000111111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000000001111111111|
Final timing values: cycles:20(adjusted 20) delay:30
WL m: 2
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00000000111111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000000000111111111|
Final timing values: cycles:20(adjusted 20) delay:31
WL m: 3
10|0000000000000000|0
11|0000000000000000|0
12|0000000000000000|0
13|0000000000000000|0
14|0000000000000000|0
15|0000000000000000|0
16|0000000000000000|0
17|0000000000000000|0
18|0000000000000000|0
19|0000000000000000|0
20|0000000000000000|0
21|0000000000000000|0
22|1111111111111111|1
DQS write leveling response transition starts in cycle:22 (adjusted 22)
DQS edge scan:
21|00000000000111111111111111111111|
DQS internal cycle alignment
|WICA:0,0|WICA:1,0|WICA:2,1|
DQS edge scan:
19|00000000000000000000000000111111|
Final timing values: cycles:21(adjusted 21) delay: 2
DQ write training
m 0|Best Vref:36
Data scan:
17|00000000000000000000000000000000|
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000013333333333000|
m 0|start cycle:22, delay:19; end cycle:22, delay:29|eye_width:10; eye center: cycle:22,delay:24
m 1|Best Vref:35
Data scan:
17|00000000000000000000000000000000|
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000000001333333333|
23|00000000000000000000000000000000|
m 1|start cycle:22, delay:23; end cycle:23, delay: 0|eye_width: 9; eye center: cycle:22,delay:27
m 2|Best Vref:39
Data scan:
17|00000000000000000000000000000000|
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000000000003333333|
23|33000000000000000000000000000000|
m 2|start cycle:22, delay:25; end cycle:23, delay: 2|eye_width: 9; eye center: cycle:22,delay:29
m 3|Best Vref:39
Data scan:
18|00000000000000000000000000000000|
19|00000000000000000000000000000000|
20|00000000000000000000000000000000|
21|00000000000000000000000000000000|
22|00000000000000000000000000113333|
23|33333300000000000000000000000000|
m 3|start cycle:22, delay:28; end cycle:23, delay: 6|eye_width:10; eye center: cycle:23,delay: 1
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40000000 0B
Write: 0x40000000-0x40020000 128.0KiB
Write: 0x40000000-0x40040000 256.0KiB
Write: 0x40000000-0x40060000 384.0KiB
Write: 0x40000000-0x40080000 512.0KiB
Write: 0x40000000-0x400a0000 640.0KiB
Write: 0x40000000-0x400c0000 768.0KiB
Write: 0x40000000-0x400e0000 896.0KiB
Write: 0x40000000-0x40100000 1.0MiB
Write: 0x40000000-0x40120000 1.1MiB
Write: 0x40000000-0x40140000 1.2MiB
Write: 0x40000000-0x40160000 1.3MiB
Write: 0x40000000-0x40180000 1.5MiB
Write: 0x40000000-0x401a0000 1.6MiB
Write: 0x40000000-0x401c0000 1.7MiB
Write: 0x40000000-0x401e0000 1.8MiB
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40000000 0B
Read: 0x40000000-0x40020000 128.0KiB
Read: 0x40000000-0x40040000 256.0KiB
Read: 0x40000000-0x40060000 384.0KiB
Read: 0x40000000-0x40080000 512.0KiB
Read: 0x40000000-0x400a0000 640.0KiB
Read: 0x40000000-0x400c0000 768.0KiB
Read: 0x40000000-0x400e0000 896.0KiB
Read: 0x40000000-0x40100000 1.0MiB
Read: 0x40000000-0x40120000 1.1MiB
Read: 0x40000000-0x40140000 1.2MiB
Read: 0x40000000-0x40160000 1.3MiB
Read: 0x40000000-0x40180000 1.5MiB
Read: 0x40000000-0x401a0000 1.6MiB
Read: 0x40000000-0x401c0000 1.7MiB
Read: 0x40000000-0x401e0000 1.8M === Initialization succeeded. ===
Proceeding ...
Memtest (basic)
OK
Memtest (random)
OKCLOUD
WebAssembly runtime for browsers
We help our customers develop seamless desktop-to-browser workflows and development environments with full filestystem access and mixed programming language capabilities. The jswasi project - Antmicro's WebAssembly runtime that can be expanded with complete applications which are served or embedded by providing a root filesystem with wasm32-wasi executables - can serve as a point of departure for such projects.
CLOUD
Scalable compute cluster software
Building on the open source software stack developed for our Scalerunner cluster, we can design control and management systems for complex compute clusters. Combining our own software components with well-known open source building blocks - including a Linux-based core, container runtime and hypervisor, caching cloud CI, monitoring, balancing and collaboration tools, we enable a fast, flexible and scalable orchestration environment capable of handling a large number of nodes efficiently.
CLUSTER #1
SAN JOSE BUILDING 4
NODE01
ACTIVENODE02
ACTIVENODE03
ACTIVENODE04
ACTIVESystem Alerts
Total alerts: 5
CLOUD
Cloud-based fleet updates and management
Our deployed_code_update RDFM fleet management solution is designed to be deployed anywhere - in the public cloud of your choice, completely on-premise or in hybrid cloud setups. We help our customers handle device management with AWS, GCP and other cloud vendors. RDFM can use Keycloak, Cognito or other tools for authentication, MinIO or S3 buckets for storage, complete with front end hosting for a friendly, bespoke web-based GUI.
RDFM Management Server
Device 1
Connected • 2m ago
Device 2
Connected • 1m ago
Device 3
Connected • 5m ago
CI Pipeline
John Doe
Build
Build successful
Test
All tests passed
Package
Package created
Delta Updates
Delta generated
Deploy
Deployed
RDFM Dashboard
Recent Actions
No recent actions
Devices Up-to-date
2/3
Active Groups
2
Latest Version
v2.1.0
Update Success Rate
98.5%
Group Status
CLOUD
Collaborative document editing infrastructure
To streamline and enhance workflows around copywriting, mailing, documentation and communications, we created MyST Editor - an open source collaborative MyST Markdown editing component. The tool incorporates a two-pane system for editing and live preview, along with comment and suggestion modes and PDF export capabilities. It offers a diff view for tracking changes, an internal spell-checker with customizable dictionaries, plugins, extensions and more. For our customers, we help integrate collaborative editing capabilities into issue trackers, version management tools and other elements of company infrastructure.
CLOUD
Custom CI Runners
Many of our and our customers' projects are hosted on public or enterprise GitHub instances, in private or public repos. While the standard GitHub runners are great for testing simpler projects, the complexity of what we work with often exceeds their capabilities, either in terms of compute power or storage. Setting up remote compute clusters managed by specialized coordinator nodes through the mechanism of custom Github runners allows us to solve these problems, e.g. in ASIC and FPGA design and verification which often rely on proprietary tooling. Custom runners also offer security for sensitive data and the ability to integrate with custom infrastructure and bespoke cloud setups.
Google Cloud Platform
Amazon Web Services
On-premises Datacenter
CLOUD
Build Results Viewers
Viewing and sharing build and test results without exposing the entire CI infrastructure is a useful capability for projects that mix proprietary and open components but want to enable public downstream consumption, external contributions and open collaboration. We can integrate any CI flow with build result viewers / remote caches based on BuildBuddy, which lets teams easily present and assess quality and performance metrics across various codebases and test suites, facilitating collaboration while ensuring secrecy where necessary.
Build results
Invocation
c1b72848-2b6c-4541-8d9f-e60a1ec6c3c0 (December 18th, 2024, 3:44:16 pm)
1066 targets evaluated on December 18th, 2024 at 3:44:16 pm for 1.32 h
Invocation
Succeded
Targets affected
1066
Broken
0
Failed
0
Failed (non-critical)
1
Successful
1065
1 target failed (non-critical)
1066 targets passed